1. Field of the Invention
The present invention relates to an array substrate for a display device, and more particularly, to an array substrate for a display device and a method of fabricating the same.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, many efforts and studies are being made to develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as a substitute for CRTs. Of these flat panel displays, active matrix type display devices are widely used.
In the active matrix type display device, pixel regions defined by gate and data lines crossing each other are located in a matrix type, a switching element, for example, a thin film transistor, and a pixel electrode are formed in each pixel region, and a data signal applied to the pixel region is controlled by the switching element.
The active matrix type display device includes an array substrate where the gate and data lines, the switching element and pixel electrode are formed.
FIG. 1 is a plan view illustrating an array substrate for a display device according to the related art.
Referring to FIG. 1, gate and data lines 20 and 30 crosses each other on a substrate 10 to define a pixel region P, and a thin film transistor T is connected to the gate and data lines 20 and 30.
The thin film transistor T includes a gate electrode 22, an active layer 26, and source and drain electrodes 32 and 34. The gate electrode 22 is connected to the gate line 20, the source electrode 32 is connected to the data line 30, and the drain electrode 34 is separated from the source electrode 32.
A pixel electrode 40 is formed in the pixel region P and connected to the drain electrode 34 through the drain contact hole 38.
A separate region SR between the source and drain electrodes 32 and 34 has a U shape. The active layer 26 is exposed through the separate region SR, and a part of the active layer 26 exposed through the separate region SR functions as a channel of the thin film transistor T.
FIGS. 2 and 3 are cross-sectional views taken along lines II-II and respectively, of FIG. 1.
Referring to FIGS. 2 and 3, the gate line 20 and the gate electrode 22 connected to the gate line 20 are formed on the substrate 10. A gate insulating layer 24 is formed on the gate line 20 and the gate electrode 22.
The active layer 26 made of intrinsic silicon is formed on the gate insulating layer 24 corresponding to the gate electrode 22, and an ohmic contact layer 28 made of impurity-doped silicon is formed on the active layer 26.
The data line 30 and the source and drain electrodes 32 and 34 are formed on the ohmic contact layer 28. A passivation layer 36 is formed on the data line 30, and the source and drain electrodes 32 and 34. The pixel electrode 40 is formed on the passivation layer 36.
The passivation layer 36 includes the drain contact hole 38 exposing the drain electrode 34, and the pixel electrode 40 is connected to the drain electrode 34 through the drain contact hole 38.
To reduce the number of production processes and production costs, the active layer 26, the ohmic contact layer 28, the source and drain electrodes 32 and 34, and the data line 30 are formed in a photolithographic process using one photo mask, which is explained further with reference to following drawings.
FIG. 4A is a view illustrating a photo mask used to form the active layer, and the source and drain electrodes of the array substrate for the related art display device, FIG. 4B is a view illustrating a photoresist pattern used to form the active layer, and the source and drain electrodes of the array substrate for the related art display device, and FIG. 4C is a view illustrating the active layer, and the source and drain electrodes of the array substrate for the related art display device.
To form the active layer 26, the ohmic contact layer 28, the source and drain electrodes 32 and 34, and the data line 30, an intrinsic silicon layer (not shown), an impurity-doped silicon layer (not shown), a metal layer (not shown) are sequentially formed on the gate insulating layer 24, then a photoresist layer (not shown) is formed on the metal layer, then a photo mask M is located over the photoresist layer to expose the photoresist layer to the light, and then the light-exposed photoresist layer is developed.
Referring to FIG. 4A, the photo mask M includes a blocking portion BA having the lowest transmittance, a semi-transmissive portion HTA having a transmittance higher than that of the blocking portion BA, and a transmissive portion TA having the highest transmittance. The blocking portion BA corresponds to the data line 30 and the source and drain electrodes 32 and 34, the semi-transmissive portion HTA corresponds to the separate region SR between the source and drain electrodes 32 and 34, and the transmissive portion TA corresponds to a region except for the data line 30, the source and drain electrodes 32 and 34 and the separate region SR.
Referring to FIG. 4B, through developing the light-exposed photoresist layer, a photoresist pattern 60 is formed.
The photoresist pattern 60 includes a first photoresist pattern 60a corresponding to the blocking portion BA, and a second photoresist pattern 60b corresponding to the semi-transmissive portion HTA. Since the transmittance of the blocking portion BA is less than that of the semi-transmissive portion HTA, a thickness of the first photoresist pattern 60a is more than that of the second photoresist pattern 60b. 
Then, the metal layer, the impurity-doped silicon layer, and the intrinsic silicon layer are sequentially etched using the first and second photoresist patterns 60a and 60b as an etching mask to form the data line 30 and a source-drain pattern (not shown).
The source-drain pattern is a pattern corresponding to the source and drain electrodes 32 and 34 and the separate region SR.
Through the etching process, an impurity-doped silicon pattern and an active layer 26 are formed below the data line 30 and the source-drain pattern.
Then, through an ashing process, the first photoresist pattern 60a is partially removed, and the second photoresist pattern 60b is completely removed. Accordingly, the source-drain pattern corresponding to the separate region SR is exposed.
Then, the source-drain pattern and the impurity-doped silicon pattern are etched using the remaining first photoresist pattern 60a as an etching mask.
Accordingly, referring to FIG. 4C, the data line 30, the source and drain electrodes 32 and 34, the ohmic contact layer 28 below the source and drain electrodes 32 and 34, the active layer 26 which is below the ohmic contact layer 28 and exposed between the source and drain electrodes 32 and 34 are formed.
The ohmic contact layer 28 and the active layer 26 are extended below the data line 30.
The reason why the separate region SR has the U shape is to improve operation capability of the thin film transistor T within a limited area. In other words, since the active layer 26 exposed through the separate region SR functions as a channel, and the current of the thin film transistor T is proportional to the width of the channel and inversely proportional to the length of the channel, so the current of the thin film transistor T can be maximized by maximizing the width of the channel and minimizing the length of the channel in a U-shpaed region.
However, referring to FIG. 4C, the U-shaped separate region SR includes a horizontal region HR, a diagonal region DR and a vertical region VR. Referring to FIG. 4A, the semi-transmissive portion HTA corresponding to the separate region SR includes a horizontal portion HA, a diagonal portion DA, and a vertical portion VA.
In an exposure process through the semi-transmissive portion HTA, light having an energy less than an energy (Eth) that is sufficiently high to initiate chemical reaction of photoresist irradiates the photoresist. Accordingly, depth of focus in the exposure process through the semi-transmissive portion HTA is abnormally shallower and astigmatism is greater than those in an exposure process through the transmissive portion TA in which light having an energy (Eop) high enough for the chemical reaction of photoresist irradiates the photoresist.
The astigmatism is an aberration that occurs because a vertical component and a horizontal component of light incident on an optical system from a light source are focused on different spots. In particular, when the U-shaped separate region SR including the horizontal region HR, the diagonal region DA, and the vertical region VR is formed using the light exposure through the semi-transmissive portion HTA, because of the astigmatism, the focus depth of the horizontal portion HA, the focus depth of the diagonal portion DA, and the focus depth of the vertical portion VA are different or common in a very narrow range.
Thus, resolution power all over the semi-transmissive portion HTA is unstable, and error margin for the light exposure process is reduced.
In other words, the photoresist pattern 60b corresponding to the semi-transmissive portion HTA is not formed with desired uniform thickness at the horizontal region HR, the diagonal region DA and the vertical region VR. Accordingly, defect such as cluster channel open or channel short occurs. When removing the first and second photoresist patterns 60a and 60b and reworking in order to correct the defect, production efficiency of the array substrate is reduced.
For example, when part of the second photoresist pattern 60b is completely removed, the channel open occurs such that the metal layer, the impurity-doped silicon layer and the intrinsic silicon layer desired to be remained in a part of the separate region SA are removed in the etching process before the ashing process. When part of the second photoresist pattern 60b is formed with a thickness greater than desired thickness, the channel short occurs such that, because part of the second photoresist pattern 60b remains after the etching process, the metal layer, the impurity-doped silicon layer and the intrinsic silicon layer desired to be removed in a part of the separate region SA remains after the etching process.